1. Field of the Invention
The present invention relates to a layout device for designing a layout of a semiconductor integrated circuit by means of automatic placement and routing, more particularly to a layout device for performing a layout change processing dedicated to alleviating a difference of percentage voltage drop in the semiconductor integrated circuit, and to a program for executing the layout device by computer.
2. Description of the Related Art
With the recent developments in miniaturization of the semiconductor production technology, thinness of wiring and narrowness of the width of wiring has been encouraged, showing a tendency to increase in interconnect resistance and interconnect capacitance. Thus, important design matter in designing semiconductor integrated circuits is to reflect parasitic elements of the wiring.
In designing power supply wiring to supply power supply voltage to the semiconductor integrated circuit, it must be remembered that voltage will fluctuate in the power supply wiring due to the parasitic elements of the power supply wiring such as consumption currents flowing through circuits, resistance, capacitance, and inductance. In particular, as an operating frequency of the semiconductor integrated circuit increases, a delay time of signal propagation changes due to a voltage drop caused by the interconnect resistance, resulting in abnormal behavior that does not meet the design rule. In this event, normal behavior would not probably be guaranteed in actual behavior, even though the normal operation is ascertained when performing a logical simulation after a layout design has finished.
Conventionally, there has been performed processing to identify by a designer an area on the layout where the aforementioned deficiencies may occur, and for changing the area to a layout that meets the design rule on the basis of the results of a voltage drop analysis.
Specifically, the voltage drop analysis is made using resistance information on respective circuit components on the layout of the semiconductor integrated circuit, and the percentage voltage drop of respective circuit components such as power supply wiring and ground wiring is expressed by stages in different colors on an image of the layout data. See Patent Document 1 (Publication of Unexamined Japanese Patent Application No. 9-55433), for instance.
There used to be restrained by a designer the voltage drop by extracting an area whose difference of the percentage voltage drop on the layout is higher, and increasing the number and the width of wiring based on display information, what is called, by applying processing to reinforce the wiring.
As mentioned above, conventionally, there used to be identified by the designer an area on the layout where deficiencies would probably occur due to the voltage drop based on the results of the voltage drop, and performed a re-layout of wiring such as power supply wiring, ground wiring, or circuit cells so as to allow the entire circuit to operate within a range permissible by the design rule. In the other words, the designer is obliged to continually grasp whatever influence is exerted upon the entire circuit caused by modifications of the layout; as well as is sometimes precluded from making a layout change that provides a proper measure for the voltage drop unless it relies upon trial and error. For these reasons, the larger circuit size to be designed, the bigger labor required for a measure for the voltage drop imposed on the designer.
In its turn, it invites a delay of the development schedule to the amount of a period of time taken for some measures for the voltage drop.